The present invention relates to an output circuit, and a data driver for a display device using the output circuit.
In recent years, as display devices, liquid crystal display devices (LCDs) that is thin, light in weight, and low in power consumption have been widespread, and frequently used for display units of mobile devices such as cell phones (mobile phones, cellular phones), PDAs (personal digital assists), handheld terminals, or notebook computers. However, in recent years, technology for increasing the screen size and complying with moving images of the liquid crystal display device have been also improved, and can realize not only the mobile application but also large-screen display devices and large-screen liquid crystal televisions of a stationary type. As those liquid crystal display devices, liquid crystal display devices of an active matrix drive system which can conduct microdisplay are used.
Referring to FIGS. 17A to 17C, a description will be generally given of a typical configuration of a thin display device (liquid crystal display device and organic light emitting diode display device) of the active matrix drive system. FIG. 17A is a block diagram illustrating a main configuration of the thin display device, FIG. 17B illustrates a main configuration of a unit pixel of a display panel in the liquid crystal display device, and FIG. 17C illustrates a main configuration of a unit pixel of a display panel in the organic light emitting display device. The unit pixels of FIGS. 17B and 17C are schematically illustrated by equivalent circuits.
Referring to FIG. 17A, the thin display device of the active matrix drive system includes a power circuit 940, a display controller 950, a display panel 960, a gate driver 970, and a data driver 980. In the display panel 960, unit pixels each having a pixel switch 964 and a display element 963 are arranged in a matrix (for example, in a color SXGA (super extended graphics array) panel, 1280×3 pixel columns×1024 pixel rows), scanning lines 961 that transmit a scanning signal output from the gate driver 970 to the respective unit pixels, and data lines 962 that transmit a gradation voltage signal output from the data driver 980 to the respective unit pixels are wired in a lattice. The gate driver 970 and the data driver 980 are controlled by the display controller 950. Necessary clock CLK and control signals are supplied from the display controller 950 to the gate driver 970 and the data driver 980, and video data is supplied to the data driver 980 as a digital signal. The power circuit 940 supplies a necessary power to the gate driver 970 and the data driver 980. The display panel 960 is configured by a semiconductor substrate, and particularly in the large-screen display devices, semiconductor substrates in which pixel switches are formed of thin film transistors (TFTs) on an insulating substrate such as a glass substrate or a plastic substrate have been widely used.
The above display device controls on/off operation of the pixel switch 964 according to the scanning signal, and supplies the gradation voltage signal corresponding to the video data to each display element 963 when the pixel switch 964 turns on to change the luminance of the display element 963 according to the gradation voltage signal, thus displaying an image.
Data for one screen is rewritten in one frame period (normally about 0.017 seconds during driving at 60 Hz), each of the scanning lines 961 is sequentially selected for each pixel row (each line) (each pixel switch 964 is turned on), and the gradation voltage signal is supplied to each display element 963 from the data line 962 through the pixel switch 964. The plural pixel rows may be selected by the scanning lines at the same time, or may be driven at a frame frequency of 60 Hz or higher.
In the liquid crystal display device, referring to FIGS. 17A and 17B, the display panel 960 is structured by the semiconductor substrate in which the pixel switches 964 and transparent pixel electrodes 973 are arranged in a matrix as unit pixels, an opposed substrate having one transparent pixel electrode 974 formed on the entire surface, and liquid crystal encapsulated between those opposed two substrates. Each of the display elements 963 includes the pixel electrode 973, the transparent pixel electrode 974, a liquid crystal capacitor 971, and an auxiliary capacitor 972. Also, a backlight is disposed on a rear surface of the display panel as a light source.
When each of the pixel switches 964 is turned on (rendered conductive) according to the scanning signal from the scanning lines 961, the gradation voltage signal is supplied to the pixel electrode 973 from the data lines 962, and the transmittance of the backlight that penetrates through the liquid crystal is changed according to a potential difference between each of the pixel electrodes 973 and the transparent pixel electrode 974. Even after the pixel switch 964 is turned off (rendered nonconductive), the potential difference can be held by the liquid crystal capacitor 971 and the auxiliary capacitor 972 for a given period.
In the drive of the liquid crystal display device, in order to prevent the deterioration of the liquid crystal, a drive (polarity reversal drive) for switching a voltage polarity (positive or negative) for each pixel normally in one frame period is conducted on a common voltage (COM) of the opposed substrate electrode 974. As typical drives, there are a dot inversion drive that is different in the voltage polarity between the adjacent pixels, and a column inversion drive that is different in the voltage polarity between the adjacent data lines. In the dot inversion drive, the gradation voltage signal of the voltage polarity different for each selection period (each data period) is output to the data lines 962. In the column inversion drive, the gradation voltage signal of the same voltage polarity for each selection period (each data period) within one frame period is output to the data lines 962.
In the organic light emitting diode display device, referring to FIGS. 17A and 17C, the display panel 960 is formed of a semiconductor substrate in which the pixel switches 964, organic light emitting diodes (organic EL) 982 each formed of an organic film held between two thin film electrode layers, and thin film transistors (TFTs) 981 that each control a current to be controlled to the organic light emitting diode 982 are arranged in a matrix as the unit pixels. Each of the TFTs 981 and each of the organic light emitting diodes 982 are coupled in series with each other between supply terminals 984 and 985 to which different supply voltages are applied, and an auxiliary capacitor 983 that holds a control terminal voltage of the TFT 981 is further provided. The display element 963 corresponding to one pixel includes the organic light emitting diode 982, the supply terminals 984, 985, and the auxiliary capacitor 983.
When each of the pixel switches 964 is turned on (rendered conductive) according to the scanning signal from the scanning lines 961, the gradation voltage signal is supplied to a control terminal of the TFT 981 from the data lines 962. A current corresponding to the gradation voltage signal is supplied to the organic light emitting diode 982 from the TFT 981, and the organic light emitting diode 982 emits light with luminance corresponding to the current for display. Even after the pixel switch 964 is turned off (rendered nonconductive), the gradation voltage signal supplied to the control terminal of the TFT 981 can be held by the auxiliary capacitor 983 to hold the light emission. The pixel switches 964 and the TFTs 981 are exemplified by re-channel transistors, but can be configured by p-channel transistors. Also, the organic EL element can be coupled to the supply terminal 984 side. Also, in the drive of the organic light emitting diode display device, the polarity inversion drive is not required unlike the liquid crystal display device, and the gradation voltage signal corresponding one-to-one to the video data is output for each selection period (each data period).
Apart from the configuration in which the organic light emitting diode display device conducts display in correspondence with the gradation voltage signals from the data lines 962 described above, the organic light emitting diode display device can conduct display upon receiving the gradation current signal output from the data driver. In the present specification, a description is limited to the configuration in which display is conducted upon receiving the gradation voltage signal output from the data driver. However, it is needless to say that the present invention is not limited to only the above configuration.
In FIG. 17A, the gate driver 970 has only to supply the scanning signal of at least a binary value whereas the data driver 980 is required to drive the respective data lines 962 according to the gradation voltage signal of the multivalued level corresponding to the gradation. For that reason, the data driver 980 includes an output circuit that amplifies the gradation voltage signal corresponding to the video data and outputs the signal to the data lines 962.
In recent years, demand for higher quality has been increased in mobile devices, notebook computers, monitors, and TVs each having the thin-screen display device. More specifically, multicolor (multigradation) of 8 bit video data (about 16,800,000 colors) or more for each of RGB, and demand for increasing a frame frequency (drive frequency for rewriting one screen) to 120 Hz or higher for an improvement in the moving picture characteristic or three-dimensional display compliance have been begun. When the frame frequency becomes N times, one data output period becomes about 1/N.
The voltage output for high precision corresponding to the multigradation and high-speed drive of the data lines are required for the data driver for the display device. For that reason, the high drive performance is required for an output circuit in the data driver 980 in order to charge and discharge the data line capacity at a high speed. Also, in order to uniformize write of the gradation voltage signals into the display elements, the symmetry of the slew rate of the data line drive waveform is also required between the charging time and the discharging time. However, the output circuit increases current consumption with the higher drive performance. For that reason, in this output circuit newly suffers from problems about an increase in the power consumption and the heat generation.
As the output circuit that drives the data line of the display device at a high speed, the following technologies are disclosed. FIG. 18 is a diagram quoting FIG. 5 of Japanese Unexamined Patent Publication No. 2009-244830 (in detail refer to the disclosure of Japanese Unexamined Patent Publication No. 2009-244830). Referring to FIG. 18, an operational amplifier circuit that configures the output circuit includes differential stages 14, 24, a positive dedicated output stage 13, a negative dedicated output stage 23, and switch circuits 3, 4, 5, 6.
The switch circuit 4 includes switches SW41 to SW44, and controls the respective couplings between terminals 41, 42, and input terminals 12, 22 of the differential stages 14, 24. The terminal 41 receives a positive voltage INP (positive DAC signal) from a positive DAC (digital-to-analog converter) not shown, and the terminal 42 receives a negative voltage INN (negative DAC signal) from a negative DAC not shown.
The differential stage 14 outputs, to input stage output terminals 51 and 52, two input stage output signals Vsi11 and Vsi12 of in-phase which are level-shifted to the magnitude corresponding to an input signal Vin1 (positive voltage INP or negative voltage INN) input through the switch circuit 4. The differential stage 24 outputs, to input stage output terminals 53 and 54, two input stage output signals Vsi21 and Vsi22 of in-phase which are level-shifted to the magnitude corresponding to an input signal Vin2 (positive voltage INP or negative voltage INN) input through the switch circuit 4. The differential stages 14 and 24 operate in a voltage range (first supply voltage range) between a negative supply voltage VSS (for example, GND potential) and a positive supply voltage VDD.
The switch circuit 5 includes switches SW51 to SW58. The switches SW51 and SW53 control the respective couplings between the input stage output terminals 51, 52 of the differential stage 14 and output stage input terminals 61, 62 of the positive dedicated output stage 13. The switches SW52 and SW54 control the respective couplings between the input stage output terminals 51, 52 of the differential stage 14 and output stage input terminals 63, 64 of the negative dedicated output stage 23. The switches SW55 and SW57 control the respective couplings between the input stage output terminals 53, 54 of the differential stage 24 and the output stage input terminals 63, 64 of the negative dedicated output stage 23. The switches SW56 and SW58 control the respective couplings between the input stage output terminals 53, 54 of the differential stage 24 and the output stage input terminals 61, 62 of the positive dedicated output stage 13.
The positive dedicated output stage 13 is coupled to the switch circuit 5 through the output stage input terminals 61 and 62, and outputs a single end signal to a terminal 11. The negative dedicated output stage 23 is coupled to the switch circuit 5 through the output stage input terminals 63 and 64, and outputs the single end signal to a terminal 21. The positive dedicated output stage 13 operates in a voltage range (second voltage range) between a supply voltage VML and the positive supply voltage VDD, and the negative dedicated output stage 23 operates in a voltage range (third voltage range) between the negative supply voltage VSS and the supply voltage VMH. The supply voltage VML is set to, for example, an intermediate voltage VSS+(VDD−VSS)/2 or lower between the negative supply voltage VSS and the positive supply voltage VDD. The supply voltage VMH is set to, for example, the intermediate voltage VSS+(VDD−VSS)/2 or higher between the negative supply voltage VSS and the positive supply voltage VDD.
The switch circuit 6 includes switches SW61 to SW64, and controls the respective couplings between input terminals (−) of the differential stages 14 and 24 that function as inverting input terminals when functioning as a feedback amplifier circuit, and the output terminals 11 and 21.
The switch circuit 3 includes switches SW31 to SW34, and controls the respective couplings between the output terminals 11, 21 of the output stages 13, 23, and an odd terminal 31, an even terminal 32. The odd terminal 31 and the even terminal 32 are coupled to respective drain lines (data lines) on an LCD panel.
The differential stages 14, 24, and the output stages 13, 23 form an amplifier circuit by the switch circuits 3, 4, 5, and 6. An operational amplifier circuit 100 (output circuit) can change the configuration of the amplifier circuit that drives the odd terminal 31 and the even terminal 32 with a change in the combination of couplings of the switch circuits 3, 4, 5, and 6. That is, during the data line drive, the coupling is switched between a pattern 1 (coupling mode 1) and a pattern 2 (coupling mode 2). In the pattern 1, the switches SW31, SW33, SW41, SW43, SW51, SW53, SW57, SW55, SW61, and SW63 are on, and the switches SW32, SW34, SW42, SW44, SW52, SW54, SW56, SW58, SW62, and SW64 are off. In the pattern 2, the states of on and off are opposite. In the pattern 1, the positive DAC signal is transmitted through a path of the terminal 41, the differential stage 14, the positive dedicated output stage 13, the output terminal 11, and the terminal 31, and the negative DAC signal is transmitted through a path of the terminal 42, the differential stage 24, the negative dedicated output stage 23, the output terminal 21, and the terminal 32. In the pattern 2, the positive DAC signal is transmitted through a path of the terminal 41, the differential stage 24, the positive dedicated output stage 13, the output terminal 11, and the terminal 32, and the negative DAC signal is transmitted through a path of the terminal 42, the differential stage 14, the negative dedicated output stage 23, the output terminal 21, and the terminal 31. The pattern 1 and the pattern 2 are switched in synchronism with the inversion of the polarity of the input voltage (output voltage).
FIG. 19 is a diagram quoting FIG. 6 of Japanese Unexamined Patent Publication No. 2009-244830. In FIG. 19, the configuration of FIG. 18 is represented by transistor level, and the switch circuits 3 and 4 in FIG. 18 are omitted. The present invention described later is applicable to the configuration of FIG. 19, and therefore this configuration will be described below. The details are referred to the disclosure of Japanese Unexamined Patent Publication No. 2009-244830.
The differential stage 14 includes NMOS transistors MN11, MN12, MN13, MN15, MN16, PMOS transistors MP11, MP12, MP13, MP15, MP16, constant current sources I11, I12, a floating current source I13, and switches SW11, SW12. The NMOS transistors MN11 and MN12 have the respective gates coupled to the switch circuit 6 and an input terminal 12 to form an Nch differential pair. The constant current source I11 receives the negative supply voltage VSS, and supplies a bias current to Nch differential pair transistors (NMOS transistors MN11, MN12). The PMOS transistors MP11 and MP12 have the respective gates coupled to the switch circuit 6 and the input terminal 12 to form a Pch differential pair. The constant current source I12 receives the positive supply voltage VDD, and supplies a bias current to Pch differential pair transistors (PMOS transistors MP11, MP12). The gates of the NMOS transistor MN11 and the PMOS transistor MP11 are coupled to the output terminal 11 or the output terminal 21 by the switch circuit 6.
The sources of the PMOS transistors MP15 and MP16 are commonly coupled to a supply terminal 15 (positive supply voltage VDD), and the drains thereof are coupled to the respective drains of the Nch differential pair transistors (NMOS transistors MN11, MN12). Also, the drain of the PMOS transistor MP15 is coupled to the floating current source I13 through the switch SW11 and the PMOS transistor MP13. Further, the gates of the PMOS transistors MP15 and MP16 are commonly coupled to the drains of the floating current source I13 and the PMOS transistor MP13. With the above configuration, the PMOS transistors MP15 and MP16 function as an active load of a folded cascade coupling. A bias voltage BP2 is applied to the gate of the PMOS transistor MP13.
The sources of the NMOS transistors MN15 and MN16 are commonly coupled to a supply terminal 16 (negative supply voltage VSS), and the drains thereof are coupled to the respective drains of the Pch differential pair transistors (PMOS transistors MP11, MP12). Also, the drain of the NMOS transistor MN15 is coupled to the floating current source I13 through the switch SW12 and the NMOS transistor MN13. Further, the gates of the NMOS transistors MN15 and MN16 are commonly coupled to the drains of the floating current source I13 and the NMOS transistor MN13. With the above configuration, the NMOS transistors MN15 and MN16 function as an active load of a folded cascade coupling. A bias voltage BN2 is applied to the gate of the NMOS transistor MN13. The switches SW11 and SW12 are normally on.
The drains of the NMOS transistor MN12 and the PMOS transistor MP16 are coupled to an input stage output terminal 51, and coupled to the positive dedicated output stage 13 (source of the PMOS transistor MP14) and the negative dedicated output stage 23 (source of the PMOS transistor MP24) through the switches SW51 and SW52. The drains of the PMOS transistor MP12 and the NMOS transistor MN16 are coupled to an input stage output terminal 52, and coupled to the positive dedicated output stage 13 (source of the NMOS transistor MN14) and the negative dedicated output stage 23 (source of the NMOS transistor MN24) through the switches SW53 and SW54. With the above configuration, two input stage output signals Vsi11 and Vsi12 corresponding to the input signal Vin1 input to the input terminal 12 are output from the drains (input stage output terminal 51) of the NMOS transistor MN12 and the PMOS transistor MP16, and the drains (input stage output terminal 52) of the PMOS transistor MP12 and the NMOS transistor MN16.
The same configuration is applied to the differential stage 24. The NMOS transistors MN11 to MN16, the PMOS transistors MP11 to MP16, the constant current sources I11, I12, the floating current source I13, the switches SW11, SW12, SW51 to SW54, bias voltages BP12, BN12, the input stage output terminals 51, 52, and the input stage output signals Vsi11, Vsi12 are replaced with the NMOS transistors MN21 to MN26, the PMOS transistors MP21 to MP26, the constant current sources I21, I22, the floating current source I23, the switches SW21, SW22, SW55 to SW58, bias voltages BP22, BN22, the input stage output terminals 53, 54, and the input stage output signals Vsi21, Vsi22, respectively.
The differential stage 14(24) has two differential pairs that receives the input signal Vin1 (Vin2), and has an active load that is folded-cascade-coupled to each of the differential pairs. The two differential pairs and the active load are each configured by a transistor different in the conduction type from each other. For that reason, two input stage output signals Vi11 and Vi12 (Vi21, Vi22) which are input from the differential stage 14(24) to the output stage 13 or 23 are in-phase signals different in the input level.
In the differential stage 14(24), when the voltage range of the input signal Vin1 (Vin2) is VSS˜VDS (sat)+VGS, only the Pch differential pairs (PMOS transistors MP11, MP12 (MP21, MP22)) operate. When the voltage range is VDS (sat)+VGS˜VDD−(VDS (sat)+VGS), both of the Pch differential pairs (PMOS transistors MP11, MP12 (MP21, MP22)) and the Nch differential pairs (NMOS transistors MN11, MN12 (MN21, MN22)) operate. When the voltage range is VDD−(VDS (sat)+VGS)˜VDD, only the Nch differential pairs (NMOS transistors MN11, MN12 (MN21, MN22)) operates. In this case, VDS(sat) is a source-drain voltage in the turn of a triode region and a pentode region of the MOS transistor included in the constant current sources I11 and I12 (I21, I22), and VGS is a gate-source voltage of the transistors (NMOS transistor MN11, MN12 (MN21, MN22), PMOS transistor MP11, MP12 (MP21, MP22)) forming the differential pair. As a result, the differential stages 14 and 24 rail-to-rail operate in an entire voltage range of VSS˜VDD of the input voltage.
The positive dedicated output stage 13 includes the NMOS transistors MN14, MN17, MN18, the PMOS transistors MP14, MP17, MP18, and phase compensation capacitors C1, C2. The drains and sources of the PMOS transistor MP17 and the NMOS transistor MN17 are mutually coupled to each other, and bias voltages BP11 and BN11 are applied to the respective gates, thereby functioning as a floating current source. The gate of the PMOS transistor MP14 is coupled to a bias constant voltage source (bias voltage BP12), and the drain thereof is coupled to one end of the floating current source (PMOS transistor MP17 and NMOS transistor MN17). The gate of the NMOS transistor MN14 is coupled to a bias constant voltage source (bias voltage BN12), and the drain thereof is coupled to the other end of the floating current source (PMOS transistor MP17 and NMOS transistor MN17). Also, the source of the PMOS transistor MP14 is coupled to the output terminal 11 through the phase compensation capacitor C11, and the source of the NMOS transistor MN14 is coupled to the output terminal 11 through the phase compensation capacitor C12.
The drain of the PMOS transistor MP18 and the drain of the NMOS transistor MN18 are coupled to each other through the output terminal 11. The gate of the PMOS transistor MP18 is coupled to one end (and the drain of the PMOS transistor MP14) of the floating current source, and the source thereof is coupled to the supply terminal 15 (positive supply voltage VDD). The gate of the NMOS transistor MN18 is coupled to the other end (and the drain of the NMOS transistor MN14) of the floating current source, and the source thereof is coupled to the supply terminal 17 to which the supply voltage VML is applied.
The same configuration is applied to the negative dedicated output stage 23. The NMOS transistors MN14, MN17, MN18, the PMOS transistors MP14, MP17, MP18, the phase compensation capacitors C11, C12, the supply terminal 15 (positive supply voltage VDD), the supply terminal 17 (supply voltage VML), and the bias voltages BP11, BP12, BN11, and BN12 are replaced with the NMOS transistors MN24, MN27, MN28, the PMOS transistors MP24, MP27, MP28, the phase compensation capacitors C21, C22, the supply terminal 16 (negative supply voltage VSS), the supply terminal 18 (supply voltage VMH), and the bias voltages BP21, BP22, BN21, and BN22, respectively.
The switch SW61 of the switch circuit 6 controls the coupling between the output terminal 11 and the differential stage 14 (NMOS transistor MN11, PMOS transistor MP11). The switch SW62 controls the coupling between the output terminal 11 and the differential stage 24 (NMOS transistor MN21, PMOS transistor MP21). The switch SW63 controls the coupling between the output terminal 21 and the differential stage 24 (NMOS transistor MN21, PMOS transistor MP21). The switch SW64 controls the coupling between the output terminal 21 and the differential stage 14 (NMOS transistor MN11, PMOS transistor MP11).
The PMOS transistor MP14 (MP24) and NMOS transistor MN14 (MN24), and the PMOS transistor MP18 (MP28) and the NMOS transistor MN18 (MN28) in the output stage 13(23) are symmetrically formed with respect to the output terminal 11(21), respectively. The output stage 13(23) outputs a single end signal based on the two input stage output signals Vsi11 and Vsi12 (Vsi21, Vsi22) of in-phase which are different in the input level to the output terminal 11(21) as the output signal Vout1 (Vout2). In this situation, idling currents of the PMOS transistor MP18 (MP28) and the NMOS transistor MN18 (MN28) are determined according to the bias voltages BP11 and BN11 (BP21, BN21).
In the operational amplifier circuit described with reference to FIGS. 18 and 19, the drive power supply can be provided according to the positive and negative dynamic range. The supply voltage range of the positive dedicated output stage 13 can be reduced to VDD˜VML (for example, VML=VDD/2) with respect to the supply voltage range VDD˜VSS of the differential stages 14 and 24. As a result, the power consumption in the positive dedicated output stage 13 is reduced. Likewise, the supply voltage range of the negative dedicated output stage 23 can be reduced to VMH˜VSS (for example, VMH=VDD/2). As a result, the power consumption in the negative dedicated output stage 23 is reduced.
FIG. 20 is a diagram quoting FIG. 3 of Japanese Unexamined Patent Publication No. 2008-271224, as an example of the output circuit having a MOS transistor and a switch diode-coupled between a gate of an output stage transistor and a supply voltage. Referring to FIG. 20, the output circuit includes an input terminal that receives an input signal, an output transistor MPout that is coupled between a supply voltage Vdd and an output terminal, and a current control circuit 10 that is coupled to the input terminal and a gate of the output transistor MPout, and controls the incoming and outgoing of a current with respect to the gate of the output transistor MPout on the basis of the input signal. The output circuit also includes a voltage generator circuit 12 (configured by two stages of PMOS transistors which are diode-coupled) coupled to the supply voltage Vdd, a switch (PMOS transistor) S2 that is coupled between the gate of the output transistor MPout and the voltage generator circuit 12, and has an open/close state controlled according to the input signal, and a capacitor C1 that is coupled between the gate of the output transistor MPout and the supply voltage gnd. A load is coupled between the output terminal and supply voltage gnd.
When a potential difference between the gate of the output transistor MPout and the supply voltage Vdd becomes a given value or lower, the switch S2 turns off regardless of the voltage level of the input signal. Also, PMOS transistors D3 and D4 which are diode-coupled between the gate of the output transistor MPout and the supply voltage Vdd, and the switch (PMOS transistor) S2 are disposed in series. A gate of the switch S2 receives the input signal (step signal) from the input terminal, and the on/off operation of the switch S2 is controlled according to the input signal.
More specifically, when the input signal changes to a high level, the transistors S11 and S12 of the current control circuit 10 turn on and off, respectively, and the switch S2 turns off. Electric charge is discharged from the capacitor C1 by the current source Is11 of the current control circuit 10 with the result that the gate voltage of the output transistor MPout gently decreases from the supply voltage Vdd to the supply voltage gnd. In this situation, when the gate voltage of the output transistor MPout decreases from the supply voltage VDD by a threshold voltage (absolute value), the output transistor MPout turns on, and the voltage of the output terminal changes to the high level.
On the other hand, when the input signal changes to a low level, the transistors S11 and S12 of the current control circuit 10 turn off and on, respectively, and the switch S2 turns on. When the switch S2 turns on, the gate voltage of the output transistor MPout is instantaneously pulled up from the supply voltage gnd to a given voltage level determined by the voltage generator circuit 12. Thereafter, electric charge is charged into the capacitor C1 by the current source Is12 of the current control circuit 10 with the result that the gate voltage of the output transistor MPout gently increases up to the supply voltage Vdd. In this situation, when the gate voltage of the output transistor MPout increases to a voltage lower than the supply voltage VDD by the threshold voltage (absolute value), the output transistor MPout turns off, and the voltage of the output terminal changes to the low level due to the load. When the gate voltage of the output transistor MPout further increases after pulling up to the given voltage level, the voltage generator circuit 12 is rendered inactive (two stages of PMOS transistors D3 and D4 which are diode-coupled turn off), and the switch S2 is also rendered inactive. That is, the switch (PMOS transistor) S2 is activated during only a period in which the input signal input to the gate is low level. Also, the switch (PMOS transistor) S2 is deactivated with the deactivation of the voltage generator circuit 12 even during the period in which the input signal is low level. The switch S2 is always held off during a period in which the input signal is high level. Also, the operation when the switch S2 is activated affects only the control of the gate voltage of the output transistor MPout that conducts the charging operation of the output terminal, and does not affect the load that conducts the discharging operation of the output terminal.